Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.
Resources for CSARCH2 (Computer Organization and Architecture 2) to help students prepare for exams and build a strong foundation in computer architecture.
GoCache – High-Performance In-Memory Cache for Go
Exerting coherency between caches with protocols in a Memory-Shared Multiprocessors system whether it has uniform memory access(UMA, symmetric) or not(non-UMA).
"vcache" is a library that provides a concurrent-safe in-memory cache to store key-value pairs.
A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.
The task is to design a "family" of three microprocessors that differ in performance and cost for the same computational task, as a project in "Computer Architecture 2" course.
This project is an implementation of cache memory with load and store instructions in Verilog.
🖥️ Explore 20 hands-on experiments to master RISC-V computer architecture concepts using the Ripes simulator for effective learning.
Global News is designed to provide users with easy access to global news in a seamless and user-friendly manner. The app focuses on delivering a smooth user experience while ensuring that users can easily find and read news articles relevant to their interests and location.
A real-time Redis monitoring dashboard with interactive charts and metrics visualization.
Um programa que simula o referenciamento do endereço da memória principal na memória cache.
Cache memory management project. Technologies and languages used: C++. University. Computer Structure.
ASP.NET Core (.NET 6) Web API + cache (Redis, Memory)
Codigo python para simular lecturas de un sistema de memoria con RAM y Caché
Small, lightweight GRPC cache memory service for use in distributed or separate systems with the ability to separate information from each system
This repository includes Logisim Evolution circuits for a 3-Bit Down Counter, BCD to Excess-3 Converter, BCD to Hex Display, 4-Bit Comparator, and Cache Memory, covering sequential logic, number conversions, and memory design. 🚀
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