cmov: add riscv32 optimised mask generation

[NicsTr]

Description of the changes brought by this commit

Currently, arm assembly is used to optimise for performance and have stronger guarantees that compiler optimisations will not insert branching during mask generation.

This commit introduces the same for the riscv32 architecture.

I managed to run successfully some of cmov's integration tests (the test in regression and the 94 tests of core_impls) on a real target: a board with an esp32c6 chip.

Discussion on the state of constant time instructions of RISC-V machines

Additionally, it may be worth alerting the user of the state of constant time instruction in RISC-V: to my knowledge, a RISC-V machine is not guaranteed to have any constant time instructions in general. Only the machines declaring that they have the Zkt extension must guarantee that the given subset of instructions described in the Zkt specification are constant time. In practice, a RISC-V machine may have constant time implementations for some or all "expected" instructions without declaring they support the Zkt extension.

To be conservative, this crate should maybe be configured not to compile if the zkt target feature is not enabled. However, this is maybe too conservative since, AFAIK, there are not a lot of chip declaring that they support this extension.

(Also, the Zicond extension provides a new instruction similar to csel or cmov. If it is welcome here, I may work on a different PR adding a new backend for targets having the zicond feature enabled)

[tarcieri]

Nice, thanks!

It would be nice if there were some way to test it in CI, although AFAICT the only riscv32 Linux target is no more: rust-lang/rust#143440